Drain Current Variability in 2-levels Stacked Nanowire Gate All Around P-type Field Effect Transistors

Donghyun Kim (1) , Sylvain Barraud (2) , Gérard Ghibaudo (1) , Christoforos Theodorou (1) , Jae Woo Lee

1 IMEP-LAHC - Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information

An experimental study of drain current statistical characteristics in two vertically stacked nanowire MOSFETs (bottom one: Omega shaped and top one: nanowire) is presented. The most critical parameter variations are identified using an advanced mismatch model that well describes the experimental results, while the impact of channel geometry is examined for every source of process variations.

Keywords: Nanowire; CMOS; FDSOI; global variability

Domains: Micro and nanotechnologies/Microelectronics

Donghyun Kim, Sylvain Barraud, Gérard Ghibaudo, Christoforos Theodorou, Jae Woo Lee. Drain Current Variability in 2-levels Stacked Nanowire Gate All Around P-type Field Effect Transistors. 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Mar 2023, Seoul, South Korea. pp.1-3, ⟨10.1109/EDTM55494.2023.10103067⟩. ⟨hal-04305370⟩