Communication Architecture Under Siege: An In-depth Analysis of Fault Attack Vulnerabilities and Countermeasures

Hongwei Zhao (1, 2) , Vianney Lapotre (1, 2) , Gogniat Guy (1, 2)

1 Lab-STICC_ARCAD - Equipe Hardware ARchitectures and CAD tools
2 UBS Lorient - Université de Bretagne Sud - Lorient

Fault attacks aim to disturb integrated circuits using physical methods to break a security system or steal information. Nowadays, a particular attention has been paid to fault attacks on SoCs (System-on-Chip). A SoC is made up of numerous IPs which are connected to each other by a communication architecture. This work focuses on a RISC-V based SoC with a wishbone bus. It aims to study the security of the bus against fault attacks. Using a simulation environment, an automate-attack script, generated by Python, targets all the registers within the bus to identify all the vulnerabilities in the communication architecture. After integrating some countermeasures, the resistance to several fault models of the extended communication structure is measured and discussed.

Domaines: Architectures Matérielles [cs.AR]; Cryptographie et sécurité [cs.CR]

Hongwei Zhao, Vianney Lapotre, Gogniat Guy. Communication Architecture Under Siege: An In-depth Analysis of Fault Attack Vulnerabilities and Countermeasures. IEEE CSR Workshop on Hardware Cybersecurity Systems (HACS), Sep 2024, London, United Kingdom. ⟨hal-04691839⟩