Inferred Fault Models for RISC-V and Arm: A Comparative Study
Résumé
With the widespread adoption of embedded systems, security issues became a major concern. In particular, such systems are vulnerable to various kinds of physical attacks, and fault injection is one of the main physical attacks. Designers and developers require fault models to predict the effects of the fault injection, so that they can analyze possible vulnerabilities and develop countermeasures against such attacks. Thus, understanding the effects of fault injection is essential to provide realistic fault models. Moreover, many of the systems currently in use or planned for future deployment incorporate either Arm or RISC-V processors. In this paper, voltage glitch campaigns have been carried out on two microcontrollers that are widely used in the embedded system market. One embeds a RISC-V core, where the other embeds an Arm Cortex-M4 core. As a result, we provide comprehensive analysis for the obtained faulty behaviors using a set of inferred fault models. We show that the presented fault models are able to explain more than 99% of the observed faulty behaviors. We also show that some of these models are applicable to both cores. Furthermore, we illustrate that some of the presented models are also comparable to state-of-the-art models that are proposed as a result of clock glitch campaigns. The presented fault models enable better understating of the fault injection effects, and thus, easing the process of analyzing vulnerabilities, and developing cost-effective countermeasures against fault attacks.
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